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-- Company: 
-- Engineer: 
-- 
-- Create Date:    29 Nov 2010 
-- Design Name: 
-- Module Name:    DISPLAY - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.all;

entity DISPLAY is
  generic (N : NATURAL := 18 );
  Port (
    CLK : in  STD_LOGIC;       -- CLK=50MHz
	 RST : in STD_logic;
    D3  : in  STD_LOGIC_VECTOR (3 downto 0);
    D2  : in  STD_LOGIC_VECTOR (3 downto 0);
    D1  : in  STD_LOGIC_VECTOR (3 downto 0);
    D0  : in  STD_LOGIC_VECTOR (3 downto 0);
    DP  : in  STD_LOGIC_VECTOR (3 downto 0);
    AN  : out STD_LOGIC_VECTOR (3 downto 0);
    CAT : out STD_LOGIC_VECTOR (7 downto 0)  --CAT(7)=DP,CAT(6)=CG,CAT(0)=CA
  );
end DISPLAY;

architecture Behavioral of DISPLAY is

 signal HEX: STD_LOGIC_VECTOR(3 downto 0);
 signal Q_REG: UNSIGNED (N-1 downto 0) := (others=>'0');
 signal sel: STD_LOGIC_VECTOR(1 downto 0);
begin

  
  with HEX SELect
  CAT(6 DOWNTO 0) <= "1111001" when "0001",   --1
                     "0100100" when "0010",   --2
                     "0110000" when "0011",   --3
                     "0011001" when "0100",   --4
                     "0010010" when "0101",   --5
                     "0000010" when "0110",   --6
                     "1111000" when "0111",   --7
                     "0000000" when "1000",   --8
                     "0010000" when "1001",   --9
                     "0001000" when "1010",   --A
                     "0000011" when "1011",   --b
                     "1000110" when "1100",   --C
                     "0100001" when "1101",   --d
                     "0000110" when "1110",   --E
                     "0001110" when "1111",   --F
                     "1000000" when others;   --0

-- CONTADOR

  process
  begin
    wait until CLK'event and CLK='1';
--	 Q_REG <= Q_NEXT;
	Q_REG <= Q_REG + 1;
  end process;
--  Q_NEXT <= Q_REG + 1;

  SEL <= STD_LOGIC_VECTOR( Q_REG(N-1 downto N-2) );

--  HEX <= D0;
   
-- MULTIPLEXOR 4 a 1 
  process(SEL, D3,D2,D1,D0)
  begin
   case SEL is
	 when "00" => HEX <= D0; AN <= "1110"; CAT(7) <= DP(0);
	 when "01" => HEX <= D1; AN <= "1101"; CAT(7) <= DP(1);
	 when "10" => HEX <= D2; AN <= "1011"; CAT(7) <= DP(2);
	 when "11" => HEX <= D3; AN <= "0111"; CAT(7) <= DP(3);
	 when others => null;
	end case;
  end process;

-- DECODER 2 a 4 para generar AN	


end Behavioral;


-- Display_inst: entity DISPLAY
--   generic map ( N => 18 );
--   Port map(
--     CLK => ,                     -- CLK=50MHz
--     RST => ,
--     D3  => ,
--     D2  => ,
--     D1  => ,
--     D0  => ,
--     DP  => ,
--     AN  => ,
--     CAT => 
--    );
